Program Structure for Heterogeneous Instruction Set Architectures

While the first non-uniform multicores (e.g., , ARM big.LITTLE) came with a unified instruction-set architecture, recent work investigates on the performance and energy benefits of heterogeneous ISAs. However, ISA diversity poses a programmability challenge, as programmers are not keen to distribute their program/data flow manually over different ISAs. Our goal is to take a step towards the seamless integration of heterogeneous ISAs into our programs.

System Model Assume that you have a multi-core CPU, where all cores have a common basic ISA (e.g. RISC-V RV64I), but some cores have additional hardware and therefore offer different instruction set extensions (e.g. vector instructions).

Our vision is to write a program that makes use of these additional instructions, but that is still able to seamlessly migrate between both types of cores.

The goal of this thesis is to manually explore these program-structure variants that use multiple, compatible versions of the same function to allow for the free migrateability (up to a certain degree).

This topic can be worked on to various degrees of detail and depth, and can thus be refined as a topic for a bachelor or master thesis or a research project.